Semiconductor devices with layers commonly contacting fins and methods of manufacturing the same
US10297601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2016 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Nov 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.