Packet processing cache
US10298496B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2017 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Oct 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W12/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data or packet processing device such as a network interface controller may include cache control logic that is configured to receive a first request for processing a first data packet associated with the queue identifier, and obtain a set of memory descriptors associated with the queue identifier from the memory. The set of descriptors can be stored in the cache. When a second request for processing a second data packet associated with the queue identifier is received, the cache control logic can determine that the cache is storing memory descriptors for processing the second data packet, and provide the memory descriptors used for processing the second packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.