Patent · US Active

Performance-aware instruction scheduling

US10303481B2 · kind B2 · utility

3Cited by

6References

7Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Peter Altevogt · Ettlingen, DE
Cedric Lichtenau · Stuttgart, DE
Thomas Pflueger · Echterdingen, DE

Key dates

Filing date	Dec 2, 2015
Grant date	May 28, 2019
Priority date	—
Expiry date	Jun 23, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/452
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.