Cedric Lichtenau
111Patents
5h-index
100Co-inventors
73Inventor score
Filing activity: Oct 16, 2003 → Mar 25, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10169451B1 | Rapid character substring searching | Electricity | 9 | Active |
| US7602874B2 | Providing accurate time-based counters for scaling operating frequencies of microprocessors | Electricity | 8 | Active |
| US10437718B1 | Computerized methods for prefetching data based on machine learned sequences of memory addresses | Physics | 7 | Active |
| US7895426B2 | Secure power-on reset engine | Physics | 6 | Active |
| US7757137B2 | Method and apparatus for on-the-fly minimum power state transition | Physics | 6 | Active |
| US7996738B2 | Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip | Physics | 5 | Active |
| US10235135B2 | Normalization of a product on a datapath | Physics | 5 | Active |
| US11269632B1 | Data conversion to/from selected data type with implied rounding mode | Physics | 4 | Active |
| US7106110B2 | Clock dithering system and method during frequency scaling | Emerging Cross-Sectional Technologies | 4 | Expired |
| US10459031B2 | Electronic circuit having serial latch scan chains | Physics | 4 | Active |
| US9858229B2 | Data access protection for computer systems | Physics | 4 | Active |
| US10324816B2 | Checking a computer processor design for soft error handling | Physics | 4 | Active |
| US9110135B2 | Chip testing with exclusive OR | Physics | 4 | Active |
| US7865749B2 | Method and apparatus for dynamic system-level frequency scaling | Physics | 4 | Active |
| US9292398B2 | Design-based weighting for logic built-in self-test | Physics | 4 | Active |
| US8471624B2 | Method for controlling the supply voltage for an integrated circuit and an apparatus with a voltage regulation module and an integrated circuit | Physics | 3 | Active |
| US10901745B2 | Method and apparatus for processing storage instructions | Physics | 3 | Active |
| US11360769B1 | Decimal scale and convert and split to hexadecimal floating point instruction | Physics | 3 | Active |
| US10303481B2 | Performance-aware instruction scheduling | Physics | 3 | Active |
| US10296294B2 | Multiply-add operations of binary numbers in an arithmetic unit | Physics | 2 | Active |
| US6989696B2 | System and method for synchronizing divide-by counters | Electricity | 2 | Expired |
| US11023205B2 | Negative zero control in instruction execution | Physics | 2 | Active |
| US9297856B2 | Implementing MISR compression methods for test time reduction | Physics | 2 | Active |
| US10747819B2 | Rapid partial substring matching | Physics | 1 | Active |
| US9923579B2 | Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.