Integrated circuit simulation with efficient memory usage
US10303828B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2017 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Jun 3, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for simulating an integrated circuit design is provided. The method includes executing a characterization tool over a first portion of a parameter space of a circuit design to form a netlist associated with the first portion of the parameter space. The method also includes forming a first sub-netlist from the netlist, selecting, for the first sub-netlist, a condition from at least one of a process, a voltage, or a temperature condition, and at least one parameter from the first portion of the parameter space. The method further includes executing a simulation of the first sub-netlist in a selected solver mode using the condition and the at least one parameter, and incorporating a result of the simulation in a circuit performance report, wherein the result is associated with the condition, with the at least one parameter, and with the first sub-netlist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.