Memory providing signal buffering scheme for array and periphery signals and operating method of the same
US10304507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2018 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Jan 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory for providing a signal buffering scheme for array and periphery signals and the operating method of the same are provided. The memory includes a plurality of columns of memory cells, a control circuit, and a control logic unit. The plurality of columns of memory cells may be connected to a local array signal generator via local control lines, which are connected to a global array signal generator via global control lines for receiving array signals. The control circuit may be connected to the memory cells for providing periphery signals. The control logic unit may be connected to the memory cells through a hierarchical structure of the global control lines and the local control lines. The control logic unit may be configured to provide the array signals and periphery signals having the same polarity to the global control lines and the local control lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.