Inventor · Bengaluru, IN

Parvinder Kumar Rana

25Patents
4h-index
39Co-inventors
59Inventor score

Filing activity: Aug 13, 2009 → Jul 26, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8120439B2 Fast start-up crystal oscillator Electricity 15 Active
US10672443B2 Methods and systems for performing decoding in finFET based memories Physics 10 Active
US8228749B2 Margin testing of static random access memory cells Physics 6 Active
US10103172B2 Method for high performance standard cell design techniques in finFET based library using local layout effects (LLE) Electricity 5 Active
US9576621B2 Read-current and word line delay path tracking for sense amplifier enable timing Physics 3 Active
US8284626B2 Voltage compensated tracking circuit in SRAM Physics 3 Active
US9001570B1 Pseudo retention till access mode enabled memory Physics 3 Active
US10998018B1 Apparatus and methods for compensating for variations in fabrication process of component(s) in a memory Physics 3 Active
US10748932B2 Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) Electricity 2 Active
US8958254B2 High performance two-port SRAM architecture using 8T high performance single port bit cell Physics 2 Active
US9496024B1 Automatic latch-up prevention in SRAM Physics 1 Active
US10566959B1 Sense amplifier flip-flop and method for fixing setup time violations in an integrated circuit Electricity 1 Active
US10304507B2 Memory providing signal buffering scheme for array and periphery signals and operating method of the same Physics 1 Active
US10651850B2 Low voltage tolerant ultra-low power edge triggered flip-flop for standard cell library Electricity 1 Active
US11776623B2 Bitline precharge system for a semiconductor memory device Physics 0 Active
US10665295B2 Static random-access memory with virtual banking architecture, and system and method including the same Physics 0 Active
US10803929B2 Static random-access memory with virtual banking architecture, and system and method including the same Physics 0 Active
US11271011B2 Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) Electricity 0 Active
US10522218B2 Methods and apparatuses to reduce power dissipation in a static random access memory (SRAM) device Physics 0 Active
US11410720B2 Bitline precharge system for a semiconductor memory device Physics 0 Active
US11017848B2 Static random-access memory (SRAM) system with delay tuning and control and a method thereof Physics 0 Active
US10715118B2 Flip-flop with single pre-charge node Electricity 0 Active
US10147493B2 System on-chip (SoC) device with dedicated clock generator for memory banks Physics 0 Active
US11790982B2 Circuits for power down leakage reduction in random-access memory Physics 0 Active
US11290092B1 Level shifter circuits Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.