Memory device and method of operating the same to prevent occurrence of read fail by adjusting bit line voltage
US10304542B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2017 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Jun 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory block including a plurality of stacked sub-memory blocks, peripheral circuits configured to perform program, read and erase operations on the memory block or on a block selected from among the sub-memory blocks, and a control logic configured to control the peripheral circuits so that, during a read operation on the memory block, if a block on which a partial erase operation has been performed is not present among the sub-memory blocks, voltages to be used for the read operation are set and so that, if a block on which the partial erase operation has been performed is present among the sub-memory blocks, the voltages to be used for the read operation are varied depending on a position of a sub-memory block that is a target of the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.