Method of forming field effect transistor (FET) circuits, and forming integrated circuit (IC) chips with the FET circuits

US10304692B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• John C. Arnold · North Chatham, US
• Robert L. Bruce · White Plains, US
• Sebastian U. Engelmann · White Plains, US
• Nathan P. Marchack · White Plains, US
• Hiroyuki Miyazoe · White Plains, US
• Jeffrey C. Shearer · Albany, US
• Takefumi Suzuki · Tokyo, JP

Key dates

• Filing date: Nov 28, 2017
• Grant date: May 28, 2019
• Expiry date: Nov 28, 2037

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P80/30
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.