Patent · US Active

I/O layout footprint for multiple 1LM/2LM configurations

US10304814B2 · kind B2 · utility

0Cited by

29References

19Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Konika Ganguly · Portland, US
Robert J. Royer, Jr. · Portland, US
Rebecca Z. Loop · Hillsboro, US
Anthony M. CONSTANTINE · Portland, US
Bilal Khalaf · Folsom, US

Key dates

Filing date	Jun 30, 2017
Grant date	May 28, 2019
Priority date	—
Expiry date	Jun 30, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An apparatus is described. The apparatus includes a package on package structure. The package on package structure includes an upper package and a lower package. One of the packages contain memory devices of a first type and the other of the packages contain memory devices of a second type. I/O connections on the underside of the upper package's substrate are vertically aligned with their corresponding, first I/O connections on the underside of the lower package's substrate. The first I/O connections are located outside second I/O connections on the underside of the lower package's substrate for the lower package.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.