Bilal Khalaf
20Patents
1h-index
19Co-inventors
46Inventor score
Filing activity: Jul 24, 2015 → Mar 29, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9871007B2 | Packaged integrated circuit device with cantilever structure | Electricity | 20 | Active |
| US11145632B2 | High density die package configuration on system boards | Electricity | 1 | Active |
| US10879152B2 | Through mold via (TMV) using stacked modular mold rings | Electricity | 1 | Active |
| US11848311B2 | Microelectronic packages having a die stack and a device within the footprint of the die stack | Electricity | 0 | Active |
| US11315843B2 | Embedded component and methods of making the same | Electricity | 0 | Active |
| US9646952B2 | Microelectronic package debug access ports | Electricity | 0 | Active |
| US11373974B2 | Electronic device packages and methods for maximizing electrical current to dies and minimizing bond finger size | Electricity | 0 | Active |
| US11329027B2 | Microelectronic packages having a die stack and a device within the footprint of the die stack | Electricity | 0 | Active |
| US10090261B2 | Microelectronic package debug access ports and methods of fabricating the same | Electricity | 0 | Active |
| US11817438B2 | System in package with interconnected modules | Electricity | 0 | Active |
| US11710674B2 | Embedded component and methods of making the same | Electricity | 0 | Active |
| US11894334B2 | Dual head capillary design for vertical wire bond | Electricity | 0 | Active |
| US10304814B2 | I/O layout footprint for multiple 1LM/2LM configurations | Electricity | 0 | Active |
| US10847450B2 | Compact wirebonding in stacked-chip system in package, and methods of making same | Electricity | 0 | Active |
| US9972610B2 | System-in-package logic and method to control an external packaged memory device | Electricity | 0 | Active |
| US11064612B2 | Buried electrical debug access port | Electricity | 0 | Active |
| US11700696B2 | Buried electrical debug access port | Electricity | 0 | Active |
| US10490516B2 | Packaged integrated circuit device with cantilever structure | Electricity | 0 | Active |
| US10475766B2 | Microelectronics package providing increased memory component density | Electricity | 0 | Active |
| US11811182B2 | Solderless BGA interconnect | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.