Patent · US Active

Semiconductor device having stressor and method of manufacturing the same

US10304840B2 · kind B2 · utility

0Cited by
7References
20Claims
0Family size

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Inventors

Key dates

Filing dateMar 30, 2016
Grant dateMay 28, 2019
Priority date
Expiry dateMar 30, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/0133

Abstract

A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.