Gate cut and fin trim isolation for advanced integrated circuit structure fabrication
US10304940B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2017 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Dec 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0149
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.