Low loss architecture for superconducting qubit circuits
US10305015B1 · kind B1 · utility
22Cited by
18References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 30, 2017 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Nov 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L24/16
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A technique relates to a structure. A first surface includes an inductive element of a resonator. A second surface includes a first portion of a capacitive element of the resonator and at least one qubit. A second portion of the capacitive element of the resonator is on the first surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.