Current doubling DC-DC converter with efficient sleep mode
US10305363B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2018 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Mar 29, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Improved current doubling DC-DC converters having an efficient sleep mode. An illustrative converter embodiment includes: a transformer, first and second inductors coupled together at a first voltage output terminal, a reserve capacitor coupled to a second output voltage terminal, a primary switch array, a secondary switch array, and a controller. The first and second inductors each have a drive terminal coupled to a respective terminal of the transformer secondary. The primary switch array operates to convert an input voltage into forward voltage pulses and reverse voltage pulses on the transformer primary. The secondary switch array selectively couples the first inductor's drive terminal to either a charge terminal of the reserve capacitor or to the second voltage output terminal. The controller at least temporarily suspends operation of the primary switch array during a sleep mode, and uses the reserve capacitor to sustain a voltage at the first voltage output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.