Pad asymmetry compensation
US10305506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2017 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Nov 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.