Temporary pipeline marking for processor error workarounds

US10310936B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Erez Barak · Hod HaSharon, IL
• Steven R. Carlough · Poughkeepsie, US
• Eyal Gonen · Nofit, IL
• Juergen Haess · Schenefeld, DE
• Silvia M. Mueller · Altdorf, DE

Key dates

• Filing date: Jan 12, 2017
• Grant date: Jun 4, 2019
• Expiry date: Jul 8, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2201/86
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring an execution unit pipeline of a processor for an event associated with a programmable instruction operational code that is predetermined to cause a stuck state resulting in an errant instruction execution. The execution unit pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking, where the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code. The marking of the pipeline is cleared based on the triggering of the clearing action, where the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.