Silvia M. Mueller
139Patents
9h-index
90Co-inventors
83Inventor score
Filing activity: Mar 19, 2003 → Aug 10, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7694112B2 | Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation | Physics | 38 | Active |
| US7461117B2 | Floating point unit with fused multiply add and method for calculating a result with a floating point unit | Physics | 18 | Active |
| US8219605B2 | Decimal floating-pointing quantum exception detection | Physics | 15 | Active |
| US8229989B2 | Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units | Physics | 14 | Active |
| US7058830B2 | Power saving in a floating point unit using a multiplier and aligner bypass | Emerging Cross-Sectional Technologies | 12 | Expired |
| US7137021B2 | Power saving in FPU with gated power based on opcodes and data | Emerging Cross-Sectional Technologies | 11 | Expired |
| US8291003B2 | Supporting multiple formats in a floating point processor | Physics | 9 | Active |
| US7290023B2 | High performance implementation of exponent adjustment in a floating point design | Physics | 9 | Expired |
| US10656913B2 | Enhanced low precision binary floating-point formatting | Physics | 9 | Active |
| US8554822B2 | Decimal adder with end around carry | Physics | 6 | Active |
| US9684514B2 | Inference based condition code generation | Physics | 6 | Active |
| US10592208B2 | Very low precision floating point representation for deep learning acceleration | Physics | 5 | Active |
| US7245159B2 | Protecting one-hot logic against short-circuits during power-on | Electricity | 5 | Expired |
| US10235135B2 | Normalization of a product on a datapath | Physics | 5 | Active |
| US8407275B2 | Fast floating point compare with slower backup for corner cases | Physics | 4 | Active |
| US8578196B2 | Zero indication forwarding for floating point unit power reduction | Emerging Cross-Sectional Technologies | 4 | Active |
| US7392270B2 | Apparatus and method for reducing the latency of sum-addressed shifters | Physics | 3 | Active |
| US8346828B2 | System and method for storing numbers in first and second formats in a register file | Physics | 3 | Active |
| US8914431B2 | Range check based lookup tables | Physics | 3 | Active |
| US7490119B2 | High speed adder design for a multiply-add based floating point unit | Physics | 3 | Expired |
| US11360769B1 | Decimal scale and convert and split to hexadecimal floating point instruction | Physics | 3 | Active |
| US9122517B2 | Fused multiply-adder with booth-encoding | Physics | 3 | Active |
| US8255726B2 | Zero indication forwarding for floating point unit power reduction | Emerging Cross-Sectional Technologies | 2 | Active |
| US8131795B2 | High speed adder design for a multiply-add based floating point unit | Physics | 2 | Active |
| US8566383B2 | Distributed residue-checking of a floating point unit | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.