System and method for power verification using efficient merging of power state tables
US10311192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2015 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Jul 31, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power verification system requires a combination of design and its power intent. A power intent (PI) input specifies the power architecture of a design through specification of power/voltage domains, their corresponding power supplies and a collection of power management devices. Power state tables (PSTs) specified in PI capture the legal combinations of power states (voltage values) for the various sets of supply nets or supply ports of a design. A power verification system requires determining the power supply relationships of voltage/power domains which requires merging of PSTs. The system described efficiently merges PSTs by iteratively selecting only a subset of PSTs that are relevant to the supply pair of interest, that are pruned initially and as the merge progresses. This provides orders of magnitude speedup and resource reduction. A user interface allows display of identified power verification failures and may include an input device for facilitating correction of at least one of the electronic circuit design and the power intent file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.