Masked gate logic for resistance to power analysis
US10311255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2016 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Dec 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of and system for gate-level masking of secret data during a cryptographic process is described. A mask share is determined, wherein a first portion of the mask share includes a first number of zero-values and a second number of one-values, and a second portion of the mask share includes the first number of one-values and the second number of zero-values. Masked data values and the first portion of the mask share are input into a first portion of masked gate logic, and the masked data values and the second portion of the mask share are input into a second portion of the masked gate logic. A first output from the first portion of the masked gate logic and a second output from the second portion of the masked gate logic are identified, wherein either the first output or the second output is a zero-value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.