High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
US10312134B2 · kind B2 · utility
3Cited by
11References
11Claims
0Family size
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Key dates
| Filing date | Aug 25, 2015 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Oct 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.