Semiconductor systems having premolded dual leadframes
US10312184B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2015 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Nov 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.