Memory cell
US10312240B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2018 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Jan 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.