Multi-chip package with selection logic and debug ports for testing inter-chip communications
US10317459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Apr 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15312
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package has an IC chip that includes logical circuitry for routing certain I/O signals to debug ports disposed on an outer surface of the microelectronic package. The I/O signals include data and command signals that are transmitted between semiconductor chips in the microelectronic package via conductive traces that are not physically accessible via with conventional debugging techniques. The logical circuitry may be configured to programmably select I/O signals based on a software input, and may be connected to the various I/O signals transmitted between the IC chip and another IC chip in the microelectronic package when a debugging of the I/O signals is enabled. Circuitry employed in conventional operation of the IC chip may also be employed to connect the logical circuitry to the various I/O signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.