Cache operation in a multi-threaded processor
US10318172B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2015 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Oct 1, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache operation in a multi-threaded processor uses a small memory structure referred to as a way enable table that stores an index to an n-way set associative cache. The way enable table includes one entry for each entry in the n-way set associative cache and each entry in the way enable table is arranged to store a thread ID. The thread ID in an entry in the way enable table is the ID of the thread associated with a data item stored in the corresponding entry in the n-way set associative cache. Prior to reading entries from the n-way set associative cache identified by an index parameter, the ways in the cache are selective enabled based on a comparison of the current thread ID and the thread IDs stored in entries in the way enable table which are identified by the same index parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.