Selective error correcting code and memory access granularity switching
US10318365B2 · kind B2 · utility
5Cited by
2References
19Claims
0Family size
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Key dates
| Filing date | Nov 2, 2012 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Jan 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example methods, systems, and apparatus to provide selective memory error protection and memory access granularity are disclosed herein. An example system includes a memory controller to determine a selected memory mode based on a request. The memory mode indicates that a memory page is to store a corresponding type of error protection information and is to store data for retrieval using a corresponding access granularity. The memory controller is to store the data and the error protection information in the memory page for retrieval using the error protection information and the access granularity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.