Patent · US Active

Determine soft error resilience while verifying architectural compliance

US10318406B2 · kind B2 · utility

2Cited by

12References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Ophir Erez · Haifa, IL
Bodo Hoppe · Tamm, DE
Divya K. Joshi · Bengaluru, IN
Gerrit Koch · Herrenberg, DE
Parminder Singh · Savanuru, IN

Key dates

Filing date	Feb 23, 2017
Grant date	Jun 11, 2019
Priority date	—
Expiry date	Aug 4, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/0778
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.