Inventor · Herrenberg, DE

Gerrit Koch

24Patents
3h-index
24Co-inventors
55Inventor score

Filing activity: Sep 16, 2012 → Jan 6, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US9274959B2 Handling virtual memory address synonyms in a multi-level cache hierarchy structure Physics 20 Active
US9245110B2 Stack entry overwrite protection Physics 6 Active
US10635555B2 Verifying a graph-based coherency verification tool Physics 4 Active
US8977823B2 Store buffer for transactional memory Physics 3 Active
US9934343B2 System and method for generation of an integrated circuit design Physics 2 Active
US10318406B2 Determine soft error resilience while verifying architectural compliance Physics 2 Active
US9928127B2 Testing a data coherency algorithm Physics 1 Active
US10282265B2 Verifying a graph-based coherency verification tool Physics 1 Active
US9959155B2 Testing a data coherency algorithm Physics 1 Active
US11099851B2 Branch prediction for indirect branch instructions Physics 0 Active
US10489296B2 Quality of cache management in a computer Physics 0 Active
US10823782B2 Ensuring completeness of interface signal checking in functional verification Physics 0 Active
US10572617B2 System and method for generation of an integrated circuit design Physics 0 Active
US9026968B2 Verification assistance for digital circuit designs Physics 0 Active
US10558510B2 Testing a data coherency algorithm Physics 0 Active
US11099919B2 Testing a data coherency algorithm Physics 0 Active
US9921906B2 Performing a repair operation in arrays Physics 0 Active
US10896118B2 Determine soft error resilience while verifying architectural compliance Physics 0 Active
US9262626B2 Stack entry overwrite protection Physics 0 Active
US10678974B2 System and method for generation of an integrated circuit design Physics 0 Active
US9928321B2 System and method for generation of an integrated circuit design Physics 0 Active
US9916195B2 Performing a repair operation in arrays Physics 0 Active
US10684857B2 Data prefetching that stores memory addresses in a first table and responsive to the occurrence of loads corresponding to the memory addresses stores the memory addresses in a second table Physics 0 Active
US10830818B2 Ensuring completeness of interface signal checking in functional verification Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.