Processor and controlling method thereof to process an interrupt
US10318452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2016 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Aug 2, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor and a control method thereof are processed. The processor includes an instruction fetch module configured to receive a first instruction of an interrupt service routine without backup of data stored in a register in response to processing of the interrupt service routine being requested, a detecting module configured to analyze the received first instruction to determine whether the data stored in the register needs to be changed, an instruction generating module configured to generate a second instruction for storing data in a temporary memory when the stored data is initially changed, an instruction selecting module configured to sequentially select the generated second instruction and first instruction; and a control module configured to perform the second instruction and the first instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.