Techniques for statistical frequency enhancement of statically timed designs
US10318676B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Apr 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques efficiently improve an integrated circuit design by simultaneously analyzing timing paths of the circuit design. A design management component can access data relating to the integrated circuit design from a design database. The design management component can perform a static timing analysis of the integrated circuit design and generate a timing path distribution, filtered analytics, and/or a probability density function associated with the integrated circuit design, wherein all of the timing paths of the integrated circuit design can be evaluated. The design management component can determine a modification to make to a cell, device, interconnection between cells or devices, or another element(s) of the integrated circuit design, based at least in part on the static timing analysis, the timing path distribution, the filtered analytics, and/or the probability density function, to generate a modified integrated circuit design, in accordance with defined design criteria.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.