Efficient techniques for process variation reduction for static timing analysis
US10318696B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2016 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Aug 2, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques efficiently improve circuit design to reduce its sensitivity to random device variation. A characterizer component can identify a subset of cells for an integrated circuit that can be representative of respective other cells of a set of cells. The characterizer component can analyze the representative cells of the subset to generate a variation profile, and can map the representative cells to physical cells used in the design of the circuit. A cell library comprising cells that are usable, have limited usage, and/or have general usage can be generated based on analysis results from the mapped cells. The circuit can be reconstructed based on the list of available cells using the cell library. The reconstructed circuit can be analyzed, and in case of a cell(s) violating a constraint, the cell(s) can be modified or enhanced to achieve target performance criteria.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.