Memory macro and method of operating the same
US10319421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2018 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Jun 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory macro includes a first set of memory cells, a second set of memory cells and a set of conductive lines. The first set of memory cells is arranged in columns and rows. Each memory cell of the first set of memory cells includes a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage. The second set of memory cells includes a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode. The set of conductive lines is coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.