Semiconductor device
US10319427B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Nov 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/014
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.