Memory with margin current addition and related methods
US10319438B2 · kind B2 · utility
1Cited by
7References
35Claims
0Family size
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Key dates
| Filing date | Oct 30, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Oct 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.