Semiconductor memory device
US10319446B2 · kind B2 · utility
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3References
20Claims
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Assignee
Inventor
Key dates
| Filing date | Jan 4, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Dec 24, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided herein is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including a plurality of memory blocks; a voltage generation circuit configured to generate a plurality of operating voltages; a decoder circuit configured to transmit the plurality of operating voltages to the memory cell array in response to a serial data signal that is sequentially inputted; and a control logic configured to generate the data signal, internal address signals and an internal clock signal in response to a command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.