Semiconductor structure and manufacturing method thereof
US10319690B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Jun 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01P3/16
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a substrate; an interconnect structure formed over the substrate and including a dielectric layer over the substrate, a first conductive member formed within the dielectric layer and a second conductive member formed within the dielectric layer; a waveguide formed between the first conductive member and the second conductive member; a first die disposed over the interconnect structure and electrically connected to the first conductive member; and a second die disposed over the interconnect structure and electrically connected to the second conductive member, wherein the waveguide is coupled with the first conductive member and the second conductive member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.