Methods for fabricating 3D semiconductor device packages, resulting packages and systems incorporating such packages
US10319696B1 · kind B1 · utility
34Cited by
4References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 10, 2018 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | May 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.