Patent · US Active

Microelectronic device package having alternately stacked die

US10319698B2 · kind B2 · utility

3Cited by

2References

15Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Bok Eng Cheah · Air Itam, MY
Min Suet Lim · Kampung Bukit Kechil, MY
Jackson Chung Peng Kong · Merang, MY

Key dates

Filing date	Nov 17, 2016
Grant date	Jun 11, 2019
Priority date	—
Expiry date	Nov 17, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/1811
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A microelectronic device package including multiple layers of stacked die. Multiple die layers in the package can include two or more die. At least two die in a first layer will be laterally spaced from one another to define a first gap extending in a first direction; and at least two die in a second layer will be laterally spaced from one another to define a second gap extending in a second direction that is angularly offset from the first direction. The first and second directions can be perpendicular to one another.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.