Poly finger fabrication for HCI degradation improvement of ultra-low-Ron EDNMOS
US10319834B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Aug 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming an EDNMOS with polysilicon fingers between a gate and a nitride spacer and the resulting devices are provided. Embodiments include forming a polysilicon layer upon a GOX layer over a substrate; forming a gate and plurality of fingers and a gate and plurality of fingers through the polysilicon layer down the GOX layer; forming an oxide layer over the GOX layer and sidewalls of the gates and fingers; forming a nitride layer over the oxide layer; removing portions of the nitride and oxide layers down to the polysilicon and GOX layers to form nitride spacers; and forming S/D regions laterally separated in the substrate, each S/D region adjacent to a nitride spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.