Fine resolution high speed linear delay element
US10320374B2 · kind B2 · utility
8Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Apr 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/0028
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor source terminal and a CTC source terminal, and a variable capacitor connected between the transistor source terminal and a constant voltage terminal where the constant voltage terminal is adapted to receive a constant voltage, and (iii) a CTC control terminal adapted to control a transconductance of the CTC by controlling a capacitance of the variable capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.