Dual-path digital-to-time converter
US10320401B2 · kind B2 · utility
7Cited by
34References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Oct 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.