Pattern based estimation of errors in ADC

US10320405B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Srinivas Kumar Reddy Naru · Markapur, IN
• Visvesvaraya Pentakota Appala · Bengaluru, IN
• Shagun Dusad · Bengaluru, IN
• Neeraj Shrivastava · Bengaluru, IN
• Viswanathan Nagarajan · Bengaluru, IN
• Ani Xavier · Kanchinakote, IN
• Rishi Soundararajan · Bengaluru, IN
• Sai Aditya Nurani · Hyderabad, IN
• Roswald Francis · Kildare, IE

Key dates

• Filing date: Mar 1, 2018
• Grant date: Jun 11, 2019
• Expiry date: Mar 1, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M1/361
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.