Dummy core plus plating resist restrict resin process and structure
US10321560B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2016 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Jan 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/308
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are exposed from the remaining layers. The PCB having an exposed inner core circuitry is formed using a dummy core plus plating resist process. The select inner core circuitry is part of an inner core. The inner core corresponding to the exposed inner core circuitry forms a semi-flexible PCB portion. The semi-flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the semi-flexible PCB portion and the remaining rigid PCB portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.