Reduced uncorrectable memory errors
US10324793B2 · kind B2 · utility
3Cited by
1References
22Claims
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Key dates
| Filing date | Mar 1, 2018 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Mar 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.