Doyle Rivers
33Patents
6h-index
24Co-inventors
65Inventor score
Filing activity: May 3, 2007 → Nov 3, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9142271B1 | Reference architecture in a cross-point memory | Physics | 20 | Active |
| US8732557B2 | Data protection across multiple memory blocks | Physics | 15 | Active |
| US9298545B2 | Data protection across multiple memory blocks | Physics | 10 | Active |
| US8203876B2 | Reducing effects of erase disturb in a memory device | Physics | 9 | Active |
| US8767487B2 | Drain select gate voltage management | Physics | 8 | Active |
| US9030906B2 | Isolating, at least in part, local row or column circuitry of memory cell before establishing voltage differential to permit reading of cell | Physics | 7 | Active |
| US10088880B2 | Thermal monitoring of memory resources | Physics | 6 | Active |
| US9136873B2 | Reduced uncorrectable memory errors | Electricity | 6 | Active |
| US7656709B2 | NAND step up voltage switching method | Physics | 5 | Active |
| US9747978B2 | Reference architecture in a cross-point memory | Physics | 5 | Active |
| US9477616B2 | Devices, systems, and methods of reducing chip select | Physics | 4 | Active |
| US10678315B2 | Thermal monitoring of memory resources | Physics | 4 | Active |
| US10324793B2 | Reduced uncorrectable memory errors | Electricity | 3 | Active |
| US8565018B2 | Reducing effects of erase disturb in a memory device | Physics | 2 | Active |
| US9996496B2 | Devices, systems, and methods of reducing chip select | Physics | 2 | Active |
| US9785603B2 | Devices, systems, and methods of reducing chip select | Physics | 2 | Active |
| US9747977B2 | Methods and systems for verifying cell programming in phase change memory | Physics | 2 | Active |
| US9721657B1 | Managing threshold voltage shift in nonvolatile memory | Physics | 2 | Active |
| US8111555B2 | NAND step voltage switching method | Physics | 1 | Active |
| US8730736B2 | NAND step up voltage switching method | Physics | 1 | Active |
| US8441860B2 | NAND step up voltage switching method | Physics | 1 | Active |
| US9934088B2 | Reduced uncorrectable memory errors | Electricity | 1 | Active |
| US10056139B2 | Managing threshold voltage shift in nonvolatile memory | Physics | 1 | Active |
| US9230666B2 | Drain select gate voltage management | Physics | 0 | Active |
| US10649656B2 | Techniques to update a trim parameter in non-volatile memory | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.