Patent · US Active

Checking a computer processor design for soft error handling

US10324816B2 · kind B2 · utility

4Cited by

10References

15Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Erez Barak · Hod HaSharon, IL
Nicol Hofmann · Stuttgart, DE
Cedric Lichtenau · Stuttgart, DE
Osher Yifrach · Holon, IL

Key dates

Filing date	Mar 8, 2017
Grant date	Jun 18, 2019
Priority date	—
Expiry date	Jul 27, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/20
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.