Semiconductor device and method for manufacturing the same
US10325807B2 · kind B2 · utility
3Cited by
5References
16Claims
0Family size
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Key dates
| Filing date | Apr 17, 2017 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Apr 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes first, second, and third metallization layers, on top of one another, that are disposed above a substrate, wherein each of the first, second, and third metallization layer includes a respective metallization structure formed in a respective dielectric layer, wherein the second metallization layer is disposed between the first and third metallization layers; and a via tower structure that extends from the first metallization layer to the third metallization layer so as to electrically couple at least part of the respective metallization structures of the first and third metallization layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.