Three-dimensional stacked vertical transport field effect transistor logic gate with buried power bus
US10325821B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2017 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Dec 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/63
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques facilitating three-dimensional stacked vertical transport field effect transistor logic gates with buried power bus are provided. A logic device can comprise a plate and a first vertical transport field effect transistor formed over and adjacent the plate. The logic device can also comprise a second vertical transport field effect transistor stacked on the first vertical transport field effect transistor. The plate can be a power layer and can be continuous within regions of the device that utilize a common voltage. The plate can be contacted from a surface of the device at intervals corresponding to the regions of common voltage. The plate can be electrically connected to ground. Alternatively, the plate can be electrically connected to a power supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.