Structure and formation method of semiconductor device structure
US10326005B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2018 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Mar 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.