Chen-Hsiang Lu
24Patents
4h-index
28Co-inventors
55Inventor score
Filing activity: Nov 15, 2013 → Aug 24, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9553090B2 | Structure and formation method of semiconductor device structure | Electricity | 22 | Active |
| US9559205B2 | Structure and formation method of semiconductor device structure | Electricity | 16 | Active |
| US9899271B2 | Structure and formation method of semiconductor device structure | Electricity | 14 | Active |
| US9450099B1 | Structure and formation method of semiconductor device structure | Electricity | 12 | Active |
| US9679850B2 | Method of fabricating semiconductor structure | Electricity | 4 | Active |
| US10686059B2 | Structure of semiconductor device structure having fins | Electricity | 2 | Active |
| US10326005B2 | Structure and formation method of semiconductor device structure | Electricity | 2 | Active |
| US10276469B2 | Method for forming semiconductor device structure | Electricity | 0 | Active |
| US10686060B2 | Structure and formation method of semiconductor device structure | Electricity | 0 | Active |
| US11404250B2 | Plasma etcher edge ring with a chamfer geometry and impedance design | Electricity | 0 | Active |
| US9613816B2 | Advanced process control method for controlling width of spacer and dummy sidewall in semiconductor device | Electricity | 0 | Active |
| US11682716B2 | Structure of semiconductor device structure having fins | Electricity | 0 | Active |
| US10867921B2 | Semiconductor structure with tapered conductor | Electricity | 0 | Active |
| US9842765B2 | Semiconductor device structure and method for forming the same | Electricity | 0 | Active |
| US10304774B2 | Semiconductor structure having tapered damascene aperture and method of the same | Electricity | 0 | Active |
| US9087793B2 | Method for etching target layer of semiconductor device in etching apparatus | Electricity | 0 | Active |
| US9177875B2 | Advanced process control method for controlling width of spacer and dummy sidewall in semiconductor device | Electricity | 0 | Active |
| US9812549B2 | Formation method of semiconductor device structure | Electricity | 0 | Active |
| US12283526B2 | Edge fin trim process | Electricity | 0 | Active |
| US12275832B2 | Fluorine-containing elastomer composition and method for making cured fluorine-containing elastomer composition | Chemistry; Metallurgy | 0 | Active |
| US10014394B2 | Structure and formation method of semiconductor device with metal gate | Electricity | 0 | Active |
| US9892957B2 | Semiconductor device structure and method for forming the same | Electricity | 0 | Active |
| US12049697B2 | Multilayer ALD coating for critical components in process chamber | Electricity | 0 | Active |
| US9704714B2 | Method for controlling surface charge on wafer surface in semiconductor fabrication | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.